Description:
Primary Skills:
- Experience with DFT / DFX
- Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc)
- Experience with Synopsys VCS and Verdi
- Bachelors in EE or CS. MS is a plus.
- Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps.
- Candidate will also be engaged in silicon bring-up and debug as needed
Responsibilities:
- This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design.
- Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes.
Qualification:
- Bachelor's degree in EE or CS. MS is a plus.
Please respond at the earliest to speed up the interview process. I will contact you if I need further details.