Asic Design Verification Engineer

Description:

Job responsibilities:

• Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
• Develop test plan and test cases to cover design feature set, follow up with stake holders at different levels of test bench
• Work closely with Design, Subsystem/SOC teams on failure debugs, code/functional coverage closure
• Debug of regression signatures and identifying bug fixes
• Responsible for Quality sign off and required documentation
• Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams
• Expertise in IP level / Sub-system level verification
• Understanding of standard bus protocol like AHB, AXI protocols would be a plus
• Having the right attitude to learn and quickly adapt to changing industry trends

Required skillset:

• Experience in HDL, verification, and general computational logic design/verification concepts
• Experience in Verilog/System Verilog and UVM/OVM
• Strong debugging, Analytical and problem-solving skills
• Experience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog, UVM, and/or other methodologies
• Experience in Scripting languages suck as Perl or Python would be a plus
• Post-Si bring-up and HW-SW debug experience would be a plus
• Communication and collaboration skills to work with a large world-wide design organization

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.