Design Engineer

Description:

The Meta Reality Labs Silicon Team focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. The Meta Reality Labs Silicon Team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, firmware, and algorithms. We are looking to hire an experienced silicon physical design technical lead to support our efforts in this regard.

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.
• Bachelor’s degree in Electrical Engineering or equivalent work experience.
• Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
• Experience working with EDA tools like DC/Genus, ICC2/Innovus, FC, Primetime, Redhawk/Voltus or Calibre.
• Understanding of RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies.