Design Verification Engineer

Description:

• Utilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.

• Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.

• Conduct full-chip and SoC simulations to validate design functionality and performance.

• Demonstrate expertise in subsystem verification, encompassing controllers and PHY components.

• Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality.

• Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe