Lead Rfic Layout Engineer

Description:

A leading-edge technology company is seeking an experienced RFIC Layout Lead to drive the design and verification of ultra low-power, high-performance Analog, RF, and Mixed-Signal ICs. This role is integral to the development of next-generation communication technologies, including Wi-Fi, Bluetooth, and Ultra-Wideband (UWB) transceivers, with a particular focus on MIMO (Multiple Input Multiple Output) systems.

This is an exciting opportunity to be at the technological forefront, guiding a high-caliber engineering team and contributing to the advancement of wireless IC solutions in sub-22nm CMOS processes. Candidates must bring a blend of technical depth, practical experience, and strong leadership to manage complex chip-level integration.

Key Responsibilities:

• Lead cross-functional planning and coordination, ensuring streamlined design-to-layout execution.

• Oversee the full layout process, including DRC, LVS, EMIR, and Self-Heating analysis.

• Take full ownership of chip-level layout, driving quality, performance, and integration standards.

• Troubleshoot and resolve layout verification issues, ensuring tape-out readiness.

• Produce detailed layout documentation and participate in design reviews.

• Mentor and lead layout engineers, maintaining high standards in top-level integration and layout practices.

Job Requirements:

• Strong experience in custom IC layout design in CMOS nodes (22nm and below).

• Expertise in analog layout strategies: matching, parasitic control, low-power design techniques.

• Knowledge of EM (electromigration), coupling, and crosstalk challenges.

• Proficiency with Cadence, Siemens DRC/LVS/Extraction, and Synopsys Custom Compiler.

• Understanding of advanced process effects (LOD, WPE), guard rings, deep N-well (DNW), and trench isolation techniques.

• Proven leadership experience guiding layout teams and managing top-level IC integration.