Physical Design Engineer V

Description:

The Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release. The candidate should have a high aptitude for design, floorplan and IO planning of complex digital top level and blocks, with experience across the complete ASIC/SOC design flow including routing, clock tree and CTS, static timing closure, EM/IR analysis and chip finishing (physical verification). The individual will closely collaborate with other digital design engineers, customers, place and route designers and supporting engineers.

Responsibilities

KEY RESPONSIBILITIES
 

• Floor-planning of moderate to very complex integrated circuits, including die sizing, Block, macro and IO placements.
• Understanding of multi-corner multi-mode (MCMM) optimizations.
• Creating power and ground distribution networks and applying unified power format (UPF.)
• Constraining and synthesis of clock trees (CTS.)
• Running routing optimization, congestion analysis and route-ability checks.
• Support of static timing analysis (STA) and execution of an engineering change order (ECO.)
• Support of technical presentations for both internal and external customers.
• Proficiency with Synopsys EDA tools, especially IC Compiler II
  
   

Qualifications

QUALIFICATIONS & EXPERIENCE
 

• Minimum ten (10) years of direct industry experience in ASIC and/or SoC design.
  • OR (14) years of experience may be considered in lieu of a Bachelors Degree.
  • OR (8) years of experience may be considered w/ a Masters Degree.
  • OR (5) years of experience may be considered w/ a PhD.
• Bachelor's degree in Electronic or Electrical Engineering/Computer Science
• A strong background in physical integrated circuit design and transistor layout architectures.
• Use of modern revision-control tools.
• Performing post-layout power analysis to include EM & IR drop.
• Experience with place & route, clock tree synthesis, timing closure, decap & filler cell insertion, density fill methodologies, DFM, and EM/IR methodologies.