Senior Dft Engineer

Description:

Media Tek is seeking a Senior DFT Engineer responsible for designing and implementing test strategies for high-performance (>1GHz) CPU subsystems using the latest DFT methodologies and techniques. The role requires defining DFT architecture, generating test patterns, simulating them in Gate Level simulations, and debugging failing patterns on silicon.

Key Responsibilities:

• Design for Test (DFT) of high-performance CPU subsystems.

• Define and implement DFT architecture to achieve all test coverage goals.

• Generate test patterns and perform Gate Level simulations.

• Debug failing patterns on silicon.

• Collaborate with global teams and communicate effectively across sites.

Required Qualifications:

• 4+ years of hands-on experience in DFT for high-speed (>1GHz) CPU subsystems, SoCs, or complex IP.

• Expertise in DFT methodologies for high-speed designs: scan insertion, scan compression, ATPG pattern generation, and at-speed testing.

• Experience defining and deploying DFT architecture for complex designs.

• Proficient in industry-standard DFT tools (preferably Synopsys DFT Compiler and Tetramax).

• Experience simulating and debugging DFT patterns using Gate Level Simulations (GLS).

• Experience running and debugging DFT patterns during Silicon Bringup.

• Excellent communication skills.

Preferred Qualifications:

• Experience with Memory BIST (MBIST) and Logic BIST.

• Proven ability to develop and deploy new DFT methodologies.

• Strong scripting skills using Perl or Tcl.

• Knowledge of JTAG.